SystemVerilog Clocking Block
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'My Design Uses Multiple Clocks'
A module/program/interface may have multiple clocks. Accordingly, it can have
as many clocking blocks as the number of clocks. This is shown in the following
example where the module design has two clocks  cp1 and
cp2. Inputs a1 and a2 as well as output b1 are
clocked by cp1. Input a3 and output b2 are clocked by
cp2. This module has two clocking modules clock1 and clock2.
module design (input cp1, input cp2,
input a1, input [7:0] a2, input a3,
output b1, output [15:0] b2
);
clocking clock1 @(posedge cp1);
input a1, a2;
output b1;
endclocking
clocking clock2 @(posedge cp2);
input a3;
output b2;
endclocking
...
endmodule
## Delay
The '##' operator defines delay in terms of number of clock cycles. For example,
##5 b2 = a2;
specifies that a2 will be assigned to b2 5 clock cycles later. At
this point, you might be asking, 'if I have multiple clocks in a block, which
clock cycle the ## operator will refer to?' The next section answers this.
Default Clocking
A clocking block can be assigned as a default clocking inside a module,
program or interface. To extend the previous example, we declare clock1
as the default clocking.
module design (input cp1, input cp2,
input a1, input [7:0] a2, input a3,
output b1, output [15:0] b2
);
default clocking clock1 @(posedge cp1);
input a1, a2;
output b1;
endclocking
clocking clock2 @(posedge cp2);
input a3;
output b2;
endclocking
...
##5 b2 = a2;
...
endmodule
In this case, since clock1 is the default clocking block, ##5 will refer
to 5 clock cycles of the clock of clock1, i.e., cp1
Conclusion
Clocking block is a powerful construct to separate the clocking behavior of
your design from its functional behavior. By separating these two behaviors,
one can easily modify one of them without disturbing the other. This helps
reduce your development time and bug rate.
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