SystemVerilog Cover Properties
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How to open up the 'black box'?
One of the major challenges in verification is to see the effectiveness of the tests that run. Functional coverage analysis solves one aspect of this problem by tracking the functional scenarios that the tests cover (more on this later). But functional scenarios are mostly about how the Design Under Test (DUT) interacts with the outside test environment. Or, in other words, functional coverage does not provide any visibility into the inside working of the DUT.
Now that was supposed to be a good thing. In today's dominant methodology the DUT is considered to be a black box and the correctness of the DUT behavior is checked only at its boundary. Your verification strategy is not supposed to know the internal working of the DUT. But what will happen if you do need to monitor something that is intricately related to the inner working of the chip? For example, how do you know if an internal FIFO is just about to be full and still works correctly? So it would be nice, if you come to know about the problem right away.
Note that this is different from looking for illegal or invalid condition that will fail a test. Those conditions need to be covered by assertions. What we are looking for here are legal and valid conditions that we are interested in monitoring to make sure that those conditions are covered in our testing.
How to do this: printf - problem with printf
From the above discussion, it is clear that we need a mechanism that will notify us of an event of interest as soon as it happens, rather than waiting for its effect to be visible. It is also clear the only way to do this would be from within RTL code.
You might be thinking 'Can't I just use $display statements in the RTL something like this?'
always @(posedge clk)
if (~rst & fifo_nearly_full)
$display ("%t: %m: Note: FIFO nearly full.\n", $time);
This mechanism provides you with a rudimentary way of monitoring the logic. There is, however, a problem in using a print statement. A print statement can not be triggered easily if you are trying to detect a complex sequence of events. To continue with our earlier example, if you need to monitor the FIFO nearly full condition when two entries are written to that FIFO within two clocks, the above 'if' condition that triggers the print statement becomes more complex.
SystemVerilog already has a mechanism for defining and detecting any sequence of events. SystemVerilog also provides a way to use the sequences to create a property. We have already used such properties to create assertions. The difference here is we need to use properties this time for creating a coverage scenario rather than an assertion scenario.
Let's take a look into how to do this. We first write the property that describes the FIFO being almost full.
property fifo_nearly_full_p (reset, clock, signal)
@(posedge clock) signal disable iff (reset);
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