Representation of Packed Types
Packed types of SystmVerilog do not have any natural counterpart
in the C domain. Nor does SystemVerilog LRM provide any direction
regarding how this would be done. This is because simulators often
optimize packed types for performance and hence the exact details
of how a packed type is treated are implementation dependent.
How does the user know how to map a packed type of SystemVerilog
domain to C domain? The answer lies in the use of two include
files: svdpi.h and svdpi_src.h.
All basic data type mappings are defined in svdpi.h file, as
well as several helper macros and functions. Almost all DPI applications
need to include this file. When an application only needs to use this
header file (and not svdpi_src.h), it is called binary
compatible - the application will run without 0 with all
simulators on that platform.
All implementation dependent features, including mapping for packed
types, are included in svdpi_src.h. An application that uses
svdpi_src.h is only source level compatible - it needs
to be recompiled before it works with another simulator on the same
Linearized and Normalized Range
All packed types of SystemVerilog domain are treated as one dimensional
entity in the C domain. For instance, consider the following declaration
reg [3:0][7:0] convoluted_memory [15:0][23:0];
From the C side, the definition of this packed array will look like:
reg [31:0] convoluted_memory [15:0][23:0];
Moreover, the C side definition also assumes a normalized range for both
packed and unpacked types. A normalized range is one where the least
significant bit is 0 for the packed arrays and the most significant bit
is 0 for unpacked arrays.
Let us assume that the original form of convoluted_memory above
reg [4:1][9:2] convoluted_memory [19:4][73:50];
After normalization (and linearization), the C side definition of the
above variable will look like:
reg [31:0] convoluted_memory [0:15][0:23];
In this part, we learnt about the basic of how to map data types between
the C and SystemVerilog sides. Based on this knowledge, next time, we will
learn how to pass arguments from the C side to the SystemVerilog side.
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