SystemVerilog Interfaces

Prev: Tasks and Functions in Interface

Parameterized Interface

Parameterizing is one more way to generalize an interface so that it can be used with a wide variety of design objects. This way parameterizing an interface is no different from parameterizing a module or a function. As a matter of fact, you will find the syntax for parameterizing an interface also closely resembles that of a module or a function. as shown in the example below. Here, the default MSB of the bus data is 31. However, when this interface is instantiated in the module top, the WIDTH parameter is changed to 15 and 63.


interface intf_AB #(WIDTH = 31) (input bit clk); 
   logic           ack;
   logic           ready;
   logic           send; 
   logic [WIDTH:0] data;
...
endinterface
...
module top;
   ...
   intf_AB #(.WIDTH (15)) narrow_intf; 
   intf_AB #(.WIDTH (63)) ultrawide_intf; 
   ...
endmodule

Specify Block and Interface

The specify block performs timing check on the signals in a module. Specifically, it allows you to check the setup timing of a signal arriving at the input port of a module and hold timing for an outgoing signal at an output port. Specify blocks are around for a long time (since early days of Verilog) and there is nothing new in it from SystemVerilog perspective. What is new, however, is the case when one of the ports in a module is an interface. In such a case, each signal in the interface becomes an available terminal, with the default direction as defined for an interface, or as restricted by a modport. Inside the specify block (which is located within a module), the signals of an interface are accessed by using their hierarchical path.

The Synthesis Question

Is the interface construct synthesizable? As always the answer will depend on the synthesizer that you use and its support for SystemVerilog. Some tools, including Synopsys Design Compiler, already supports interface as a synthesizable construct. It is expected as the support for SystemVerilog increases in the future, more and more synthesizer will implement interface as a synthesizable construct.

Prev: Tasks and Functions in Interface

Share/Save/Bookmark




We Recommend


Book of the Month