Specify Block and Interface
The specify block performs timing check on the signals in
a module. Specifically, it allows you to check the setup timing of a
signal arriving at the input port of a module and hold timing for an
outgoing signal at an output port. Specify blocks are around for a
long time (since early days of Verilog) and there is nothing new
in it from SystemVerilog perspective. What is new, however, is the
case when one of the ports in a module is an interface. In such a
case, each signal in the interface becomes an available terminal,
with the default direction as defined for an interface, or as
restricted by a modport. Inside the specify block (which is located
within a module), the signals of an interface are accessed by using
their hierarchical path.