Property Specification Language Tutorial

(Part 1)

by

Ajeetha Kumari

Next: Anatomy of a PSL Assertion

Property based verification is picking up momentum among the design and verification community. PSL has emerged as one of the standard assertion languages and is on its way to becoming an IEEE standard. This tutorial is intended to get you quickly started on the language.

What is an assertion language

An assertion or property language captures the design behavior spread across multiple clock cycles in a concise, unambiguous manner. It is a great way to describe control intensive design behaviors, pipelines, latencies etc. While traditional RTL captures the cycle-by-cycle behaviour, it is way too detailed (and error prone) to describe properties at a higher level. While the bottom most layer of a property is still a boolean expression, a property language adds means to express temporal relationships among those expressions and provides operators to capture complex design behaviors in a concise manner.

PSL - Property Specification Language is designed to capture design intent in an executable, formal, unambiguous manner. It is developed as more "evolutionary" language than re-inventing wheel. It uses many of the underlying HDL operators and expression syntax to build the boolean expressions in properties rather than defining its own syntax and semantics for the same. However, where-ever required, it defines its own syntax to build complex temporal relationship among the boolean expressions.

Next: Anatomy of a PSL Assertion


Ajeetha Kumari is currently working as a Design Verification Consultant based in Bangalore, India. Her interests include ABV (PSL/SVA), and SystemVerilog. She has co-authored two books on PSL and SVA focussing on the methodology and language. She maintains a verification centric site. She can be reached at: ajeetha - at - noveldv.com

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