How to display the strength of a net and its drivers
Vineyard Research Inc.
Sometimes it is useful to see the following information about a
net all in one place.
(During the debugging of a logic, if you ever had to chase an X on a net,
you know what I mean!)
- The logic value of the net
- Its strength value
- How the net has got these values: the logic and strength
values of its drivers.
Unfortunately, there is no standard system call to find out what are
the drivers of a net and what are their strength values. Verilog-XL
provides a non-standard system call $showvars, which finds out the
drivers of a net. But there is no system call to find out the origin
of propagating Xs.
We are now going to see how to write such a PLI application.
Note that, the term "strength" makes sense only for a wire - a bus
or a reg can not have any strength. Since, strength makes more sense
for gate level design rather than RTL or behavioral design, our
system call $strength will assume a gate level model for
the input design.
The following Verilog program shows how to use such a call.
myand u1 (q, 1'b1, 1'b1);
myand u2 (q, 1'b0, 1'b1);
module myand (c, a, b);
and m1 (c, a, b);
The code listing for $strength is shown below.
if (tf_typep(1) != tf_readonly)
tf_error("The parameter must be a scalar net");
handle net = acc_handle_tfarg(1), driver = null;
io_printf(" Signal: %s, Strength: %s\n",
acc_fetch_value(net, "%v", null));
io_printf(" Driving Strengths:\n");
while (driver = acc_next_driver(net, driver))
io_printf(" %s\t\t %s\n",
acc_fetch_value(driver, "%v", null));
Notice that the net q in our example should be at x,
as there is a contention between the outputs of the two AND
Here is the output of the Verilog program:
Signal: top.q, Strength: StX