Structure Type in SystemVerilog

It has been there in VHDL all along, and now SystemVerilog has it too. In this article, you will learn what the new datatypes 'structure' and 'union' are and how they can help you in writing better and more legible code. It will also help you in answering the million dollar question (or, at least whatever dollar amount a license of your synthesis tool costs): are these constructs synthesizable?

Those Pesky Structure and Union Types

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A structure is a user-defined collection of various datatypes. Each of the constituent members of a structure is also called its field. These fields can be either standard datatypes (such as, int, time, logic, bit, to name a few) or, they can be user-defined types (using SystemVerilog typedef) and, possibly, another structure.

Essentially, a structure is a set of some inter-related data. Theoretically, the members of a structure can be defined separately and you can still work with all of them. But, wrapping them together in a structure helps you to organize these inter-related variables.

As an example below (note the keyword struct), in the structure floating_pt_num, both characteristic and mantissa are 32-bit value of type bit.

struct { 
   bit [31:0] characteristic; 
   bit [31:0] mantissa; 
} floating_pt_num; 

Alternately, we could also write

typedef struct { 
   bit [31:0] characteristic; 
   bit [31:0] mantissa;
} flpt; 

flpt floating_pt_num;

Here, first we define a type flpt using typedef ad then use that to declare the variable floating_pt_num.

Assigning a value to one or more fields of a structure is stright- forward.

floating_pt_num.characteristic = 32'h1234_5678;
floating_pt_num.mantissa       = 32'h0000_0010; 

As mentioned, you can define a structure whose fields are other structures themselves.

typedef struct {
   flpt x; 
   flpt y; 
} coordinate;

The datatype union is very similar to a structure, but only one of the fields will be valid at a given point of time.

For instance, a variable point can be defined as the union shown below where only one of xy or r_theta is valid.

union {
   coordinate xy;
   coordinate r_theta;
} point; 

Those of you who are already familiar with C style structure and union types, will no doubt find the SystemVerilog definitions for structure and union to be very similar to their counterparts in C. However, various other unique features of SystemVerilog data types can also be applied to structure and unions. For example, it is possible to 'pack' a structure in memory without gaps between its bit fields. This may be useful for fast access of data during simulation and possibly smaller footprint of your simulation binary.

To do this, you need to use the packed keyword in the definition of a structure.

typedef struct packed { 
   bit [31:0] characteristic;
   bit [31:0] mantissa; 
} flpt; 

The beauty of packed structures is that one or more bits from such a structure can be can be selected as if it were a pcaked array. For instance, flpt[47:32] in the above declaration is same as c[15:0].

Next: Structures and Unions in your design


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