SystemVerilog Assertion


Part 1: The Ground Work

Next: Concurrent assertion

as·sert \&-'s&rt, a-\ vt [L. assertus, pp of asserere, from ad- + serere to join
1 : to state or declare positively and often forcefully or aggressively
2 a : to demonstrate the existence of
2 b : POSIT, POSTULATE

Merriam-Webster Dictionary.

What is An Assertion?

An assertion in the context of a programming language is a statement that validates assumptions or checks conditions in a program. An assertion, for example, can notify you if some legal or illegal combination of values of internal program variables has occured. In pseudo-code, an assertion looks as follows:

 
if (condition) then 
   take_action
An assertion is an 'observer' - it observes the state of the program and, if built that way, can block further execution of the code, but it can not alter the program itself.

SystemVerilog has integrated a set of constructs that helps you to build assertions and closely couple them with the rest of your design or verification code. One of the main features of SystemVerilog assertion constructs is that they are part of the language itself. This means you can use them inline with other language constructs without any need to create special pragmas or similar restrictions.

Types of SystemVerilog Assertion

There are two main types of SystemVerilog assertions: (1) immediate and (2) concurrent assertions. The following sections explain what they mean.

Immediate Assertions

An immediate assertion checks if an expression in a procedural block is true (i.e., its value is 1) at any given instance of time. If it is, an associated block of code (commonly called a 'pass block') is executed. If the expression is false (i.e. its value is one of 0, X or Z), an alternate block of code (a 'fail block') is executed. Thus, an immediate assertion is very similar to an if-else statement.

An immediate assertion has the following form.

assert (expression)
   pass_block;
else 
   fail_block;

An example of an immediate assertion is shown below.

assert (cond1 & cond2) 
   $display ("Pass..."); 
else 
   $display ("Fail...");
You can specify a label for an immediate assertion (making it a named block).
my_assert: assert (cond1 & cond2) 
              $display ("Pass..."); 
           else 
              $display ("Fail...");

The else part and its associated fail block are optional. If an expression is not true and it does not have an associated else part, verification tools automatically register that as an error. However, with an else statement, you can do more than just to display that the assertion has failed. You can specify whether this failure should be regarded as a fatal run time error, a regular run time error, a warning or just a notification. This is done by using one of the system tasks $fatal, $error, $warning or $info. Specifying the severity of a failure this way allows a tool to take appropriate action on how to register this failure. All of these system tasks have exactly the same format as $display. The following code segment shows how to use $warning as an example.

my_assert: assert (cond1 & cond2) 
              $display ("Pass..."); 
           else 
              $warning("Fail...");

Next: Concurrent assertion

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