# SystemVerilog Assertion

## Part 2: Sequence - An Introduction

In Part 1 of this series, we saw how an immediate assertion is useful for checking condition at a given instance of time, and also how a concurrent assertion checks for a sequence of events over a period of time. We also learnt about Boolean Expression Layer, the most basic and fundamental of the four layers of concurrent assertions. In this Part 2, we will look into the Sequence Layer, which defines, as the name aptly implies, a sequence that the assertion is supposed to check.

## The Sequence Layer

The Sequence Layer in concurrent assertion is built on top of the Boolean Expression Layer. As the name suggests, the Sequence Layer describes a sequence made of a series of events and possibly of other sequences. A sequence is the most basic construct for defining any concurrent assertion. So the role of the Sequence Layer is extremely important for concurrent assertion.

Events, of course, always occur along time. But while defining a sequence, the absolute timing relationship among the events are not always known. If the events occur in a simple chain along time (as it was in our previous example involving reset, req and ack), when the absolute timing relationship among events are known, the sequence is called a linear sequence. However, in real designs, often sequences can not be ordered according to their absolute time of occurances. The events trigger one another and thus absolute time of occurances are not known before hand. This leads to non-linear sequences, where multiple sequences interact with and control one another.

## The Sequence Block

The main purpose of the Sequence Layer is to define one or more sequences. The SystemVerilog syntax defines a sequence in a sequence-endsequence keyword pair with an associated name. The actual chain of events is defined within such a sequence block. A linear sequence is easy to define using SystemVerilog ## operator. The ## operator defines delays in terms of clock ticks - for example, ##5 means a delay of 5 clock ticks as in the example below between signal ~reset and req. The following example shows how to define Sequence 1 of our earlier example.

```sequence Sequence1;
~reset ##5 req;
endsequence
```
Similarly, Sequence 2 defined earlier can be expressed as follows.
```sequence Sequence2;
req ##2 ack;
endsequence
```
And, finally, the two sequences can be written together as follows. Note the use of one sequence (Sequence1) inside another (MegaSequence).
```sequence MegaSequence;
Sequence1 ##2 ack;
endsequence
```

A sequence can be instantiated in any of the following blocks.

## The ## operator

The ## operator in SystemVerilog can be used in a number of ways. You have already seen the basic application of ## in the above examples. One important proporty of ## is that it can be used to join expressions consisting of events (such as req or (~req)) as well as two sequences. Here are some other ways to use the ## operator. In all these examples, a, b etc. can be an event, a signal or another sequence.

1. The operator ## can be used multiple times within the same chain.

```   a ##1 b ##2 c ##3 d
```

2. You can indefinitely increase the length of a chain of events using ## and 1'b1. The example below extends the previous chain of events by 50 clocks.

```   a ##1 b ##2 c ##3 d ##50 1'b1
```

3. The following indicates b starts on the same clock when a ends.

```   a ##0 b
```

4. This means b starts one clock after a ends.

```   a ##1 b
```

5. You can use an integer variable in place of the delay.

```   a ##delay b
```

6. The following means b completes 2 clock ticks after a completes (regardless of when b starts).

```   a ##2 b.ended
```

7. You can specify a range of absolute delays too.

```   a ##[1:4] b
```
You can also use a range of variable delays.
```   a ##[delay1:delay2] b
```

8. The symbol \$ in a delay range indicates that a signal or event will 'eventually' occur.

```   a ##[delay1:\$] b
```

### Can You?

Once the two sequences that we defined earlier are all written and tested, a new hardware specification came up at the request of an important customer. Now it seems, once the reset is de-asserted, the signal req is asserted anytime within 5 to 7 clocks. And because of a bug, the ack assertion happens anytime after 2 clocks after req is asserted. Can you write an assertion to do this?

 Join Verification Management Group

Shop Amazon - Contract Cell Phones & Service Plans

 Book of the Month