# SystemVerilog Assertion

## Sequence and Clock

One of the most important aspects of concurrent assertion (and thus of sequences) is that it always works at a clock edge. All expressions are evaluated at an edge and all actions corresponding to the values of those expressions are also carried out at an edge. If an expression changes value at an intermediate point of a clock cycle, concurrent assertion is blind to that change. This has been done so that a concurrent assertion samples only stable values of all variables.

### Implied Clock

So, it is now natural for you to ask which clock the sequence Sequence1 (reproduced below from our earlier example) for calculating ##5 uses since there is no clock in the sequence at all?

```sequence Sequence1;
~reset ##5 req;
endsequence
```
The same question holds true for Sequence2. The answer to this is that both this sequences use something known as 'implied clock' - a clock that is supplied to these sequences when they are instantiated by an element of layers above the sequence layer (property layer, for example). Whichever clock that higher level element has, the sequence inherits the same.

### Using Clock inside a Sequence

Although we are already using an implied clock in Sequence1, a clock reference in a sequence does not always have to be implied. If you know the name of the implied clock, you can use it directly inside your sequence.

```sequence Sequence3;
@(posedge clk_1) // clock name is clk_1
s1 ##2 s2; // two sequences
endsequence
```
In the above example, as we saw in a previous example, Sequence3 uses two subsequences s1 and s2. While subsequences can be nested (s1 uses subsequence s2, s2 uses subsequence s3 and so on), beware of the cross-coupled subsequences - for example, s1 uses s2 as its subsequence and s2 uses s1 as its subsequence - that causes infinite looping.

A sequence also can have multiple clocks, a subject that we will come back to in the later part of this series.

## Sequence Operations

Now we will discuss operations that can be performed on a sequence or between two sequences. Just as x+y, where x and y are integers, produces a new integer (their sum), these operations produces a new sequence from one or more existing sequences. We are already familiar with one such operator - the cycle delay operator '##' that 'joins' two sequences (or one sequence and an event) with a number of clock cycles between them.

There are three main categories of sequence operations as Figure 2 shows.
 Category Operators Associativity Repetition [* ] [= ] [-> ] - Cycle Delay ## Left Match throughout, within, intersect, and, or right for throughout, left for others

In this Part 2, we will discuss the repetition operators. In the next part, we will look into the match operators.